Data Structures and Algorithms

2611 Submissions

[2] viXra:2611.0031 [pdf] submitted on 2026-11-11 21:18:15

Hardware Integration of Nfns and SBNS Numeral Systems in a Fault-Tolerant Neuromorphic Processor Architecture

Authors: Andrey V. Voron
Comments: 13 Pages. (Note by viXra Admin: Further repetition will not be accepted!)

This paper investigates the microarchitectural principles and technological prospects of designing a fundamentally new class of computing devices — a hybrid fault-tolerant neuromorphic processor. The feasibility of deep hardware integration of the New Fibonacci Numeral System (NFNS) and the Scaled Bergman Numeral System (SBNS) on a single semiconductor die is substantiated. It is demonstrated that due to the identical nature of their underlying mathematical principles (representation of weights via fractions, Fibonacci confluent/convoluted rules), both systems can share up to 85—90% of the physical area of the arithmetic logic unit (ALU) and utilize a unified hardware parity filter. A mechanism for dynamic on-the-fly switching of the computational basis within a single clock cycle via a configuration register depending on the specific application task is described. A technological forecast is formulated, according to which the integer NFNS mode ensures noise immunity and error control (bit-flips) in critical discrete environments (aerospace, cryptography), while the SBNS mode, leveraging the Truncation Symmetry Theorem, eliminates the accumulation of rounding errors and optimizes the bit-width of the significant register mantissa, serving as an ideal foundation for neuromorphic AI accelerators.
Category: Data Structures and Algorithms

[1] viXra:2611.0017 [pdf] submitted on 2026-11-05 21:23:27

Implementation of Basic Arithmetic Operations in the Scaled Bergman Number System (SBNS)

Authors: Andrey V. Voron
Comments: 5 Pages.

The paper examines the algorithmic specifics of performing basic arithmetic operations in the Scaled Bergman Number System (SBNS) with a fixed weight scale factor of k = 0.2. The mechanisms for implementing linear operations (addition and subtraction) are analyzed, and the specific hardware phases for executing non-linear operations — multiplication and division under conditions of a scaled basis shift — are decomposed and described in detail. Using a concrete example of bitwise numerical multiplication, the operation of a two-phase arithmetic logic unit (ALU) utilizing a cyclic multiplier by a constant of 5 for scale code correction is demonstrated. A three-stage division cycle is described that employs a hardware parity filter to eliminate redundancy and ensure a fast, unambiguous bitwise comparison operation.
Category: Data Structures and Algorithms