S.jhansi Lakshmi

[1] viXra:1405.0048 submitted on 2014-05-07 01:34:19, (478 unique-IP downloads)

Minimizing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme

Authors: A.saisudheer, V. Murali Praveen, S.jhansi Lakshmi
Category: Data Structures and Algorithms